Title :
Tagged probabilistic simulation provides accurate and efficient power estimates at gate level
Author :
Chih-Shun Ding ; Pedram, M.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
In this paper we summarize the techniques employed in tagged probabilistic simulation (TPS) to perform gate level power estimation. A prominent feature of TPS is the use of tagged probability waveforms to provide a more compact, yet detailed, waveform representation. This helps resolve several important shortcomings of conventional probabilistic simulation techniques in which the logical waveforms of each node are represented by a single probability waveform. Experimental results show that TPS can provide accuracy levels of 10-15% compared to circuit simulation in dynamic power estimation with run times orders of magnitude faster.
Keywords :
circuit analysis computing; logic CAD; logic design; probability; waveform analysis; gate level power estimation; logical waveforms; tagged probabilistic simulation; Capacitance; Circuit simulation; Computational modeling; Contracts; Energy consumption; Logic; Probability; Semiconductor device modeling; Sequential circuits; Steady-state;
Conference_Titel :
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-3036-6
DOI :
10.1109/LPE.1995.482456
