Title :
A 3.3 V quad digital signaling interface transceiver
Author :
Anidjar, J. ; Brauns, G.T. ; Lakshmikumar, K.R. ; Mastrocola, A.R. ; Ramachandran, R. ; Sherry, D.E. ; Tham, K.M. ; Tracy, P.H. ; Werner, S.A. ; Dwarakanath, M.R.
Author_Institution :
AT&T Bell Labs., Allentown, PA, USA
Abstract :
This paper describes the low-power techniques used to design the Clock/Data recovery, Jitter Filter and the high current Line Driver circuits in a Quad Line Interface for DS1/CEPT applications.
Keywords :
clocks; driver circuits; electronic switching systems; jitter; telecommunication signalling; transceivers; 3.3 V; DS1/CEPT applications; clock/data recovery; high current line driver circuits; jitter filter; low-power techniques; quad digital signaling interface; telephone central office equipment; transceiver; Clocks; Driver circuits; Filtering; Frequency; Jitter; Pulse circuits; Quantization; Space vector pulse width modulation; Timing; Transceivers;
Conference_Titel :
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-3036-6
DOI :
10.1109/LPE.1995.482458
