An automatic-power-save cache memory for low-power RISC processors

Author

Shimazaki, Y. ; Ishibashi, K. ; Norisue, K. ; Narita, S. ; Uchiyama, K. ; Nakazawa, T. ; Kudoh, I. ; Izawa, R. ; Yoshioka, S. ; Tamaki, S. ; Nagata, S. ; Kawasaki, I. ; Kuroda, K.

Author_Institution

Div. of Semicond. & Integrated Circuits, Hitachi Ltd., Tokyo, Japan

fYear

1995

fDate

9-11 Oct. 1995

Firstpage

58

Lastpage

59

Abstract

A test chip was fabricated using 0.5-/spl mu/m CMOS technology and the cache memory operated at 60 MHz with a supply voltage of 3.3 V, and it operated with a power dissipation of 8 mW with a supply voltage of 2.5 V at 10 MHz. Automatic-power-save architecture, a pulsed word technique and an isolated bit line technique reduced the power dissipation of the cache memory to almost 60% at a frequency of 60 MHz and to 20% at 10 MHz by these techniques.

Keywords

CMOS memory circuits; cache storage; memory architecture; microprocessor chips; reduced instruction set computing; 0.5 micron; 10 to 60 MHz; 2.5 to 3.3 V; 8 mW; CMOS chip; automatic-power-save architecture; cache memory; isolated bit line technique; low-power RISC processor; pulsed word technique; CMOS technology; Cache memory; Circuits; Clocks; Frequency; Large Hadron Collider; Phase locked loops; Power dissipation; Reduced instruction set computing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics, 1995., IEEE Symposium on

Conference_Location

San Jose, CA, USA

Print_ISBN

0-7803-3036-6

Type

conf

DOI

10.1109/LPE.1995.482463

Filename

482463