A universal Pezaris array multiplier generator for SRAM-based FPGAs

Author

Stohmann, Jörn ; Barke, Erich

Author_Institution

Inst. of Microelectron. Syst., Hannover Univ., Germany

fYear

1997

fDate

12-15 Oct 1997

Firstpage

489

Lastpage

495

Abstract

A new approach to implement fast array multipliers of any word length in SRAM-based FPGAs is presented. The proposed method is based on a generic FPGA model and, therefore, suitable for most commercial FPGA devices. Taking the logical structure of the multiplier into account, technology mapping including adaptive structure generation as well as signal flow driven placement and automatic partitioning are efficiently performed yielding implementations of higher performance and better resource utilization than previously published

Keywords

arrays; field programmable gate arrays; logic CAD; multiplying circuits; SRAM-based FPGAs; adaptive structure generation; automatic partitioning; commercial FPGA devices; fast array multipliers; generic FPGA model; logical structure; resource utilization; signal flow driven placement; technology mapping; universal Pezaris array multiplier generator; Circuit synthesis; Delay; Digital signal processing; Field programmable gate arrays; Logic arrays; Logic devices; Partitioning algorithms; Routing; Signal processing algorithms; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-8206-X

Type

conf

DOI

10.1109/ICCD.1997.628913

Filename

628913