Title :
55-mW 300-MHz analog-digital converters using digital VLSI technology
Author :
Sutardja, P. ; Tang, D.D. ; Altieri, J. ; Thon, L.E. ; Coleman, G. ; Subbanna, S. ; Sun, J.Y.-C.
Author_Institution :
IBM Corp., San Jose, CA, USA
Abstract :
To evaluate the potential of scaled CMOS technologies for analog application, a very high speed analog-digital converter (ADC) was designed and fabricated using a 3.6-V, 0.8-micron and a 2.5-V, 0.5-micron digital CMOS technology. The former was designed for sampling at 200 MHz and the latter at 300 MHz worst case. This paper describes the design issues and the performance of the ADC fabricated in two generations of CMOS.
Keywords :
CMOS integrated circuits; analogue-digital conversion; very high speed integrated circuits; 0.5 micron; 0.8 micron; 2.5 V; 3.6 V; 300 MHz; 55 mW; VLSI; design; digital CMOS technology; very high speed analog-digital converter; Analog-digital conversion; CMOS technology; Circuits; Clocks; Decoding; Frequency; MOSFETs; Resistors; Sampling methods; Very large scale integration;
Conference_Titel :
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-3036-6
DOI :
10.1109/LPE.1995.482467
