• DocumentCode
    316860
  • Title

    Transistor-level sizing and timing verification of domino circuits in the Power PCTM microprocessor

  • Author

    Dharchoudhury, A. ; Blaauw, D. ; Norton, J. ; Pullela, S. ; Dunning, J.

  • Author_Institution
    High Performance Design Technol., Motorola Inc., Austin, TX, USA
  • fYear
    1997
  • fDate
    12-15 Oct 1997
  • Firstpage
    143
  • Lastpage
    148
  • Abstract
    This paper describes a tool called Focus that is currently being used for the timing verification and siting of domino CMOS circuits in a Power PCTM microprocessor. Domino CMOS circuits introduce more complex timing and sizing requirements compared to conventional static circuits. This paper shows how these requirements are addressed in Focus. Some case studies involving the application of Focus on production circuits are also described
  • Keywords
    CMOS logic circuits; SPICE; microprocessor chips; timing; CMOS circuits; Focus; Power PCTM microprocessor; case studies; domino circuits; static circuits; timing verification; transistor-level sizing; CMOS technology; Circuit simulation; DH-HEMTs; Delay; Microprocessors; Phase change materials; Production; Robustness; Semiconductor device modeling; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-8186-8206-X
  • Type

    conf

  • DOI
    10.1109/ICCD.1997.628861
  • Filename
    628861
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=316860