Title :
A device design study of 0.25 /spl mu/m gate length CMOS for 1 V low power applications
Author :
Nandakumar, M. ; Chatterjee, Avhishek ; Rodder, M. ; Chen, I.-C.
Author_Institution :
Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A 0.25 /spl mu/m gate length CMOS with multiple-V/sub T/ is proposed for 1 V low power applications; low-V/sub T/ devices for critical paths, and high-V/sub T/ devices for the rest of the circuit. Various device designs, viz. super-steep retrograde (SSR), SSR with surface counter doping (CD), conventional, and conventional with CD, to realize the high- and low-V/sub T/ devices are experimentally evaluated by comparing the nominal I/sub DRIVE/ and V/sub T/ rolloff. It is found that the SSR+CD channel profile is optimum for low-V/sub T/ CMOS, while SSR and conventional are optimum for high-V/sub T/ NMOS and PMOS, respectively. The power and performance tradeoffs for these devices are evaluated using a verified figure-of-merit and SPICE simulations, and the results are found to be reasonably comparable to published data.
Keywords :
CMOS integrated circuits; SPICE; circuit analysis computing; circuit optimisation; integrated circuit design; 0.25 /spl mu/m gate length CMOS; 0.25 mum; 1 V; SPICE simulation; V/sub T/ rolloff; channel profile; critical paths; device design study; figure-of-merit; high-V/sub T/ devices; low power applications; low-V/sub T/ devices; power/performance tradeoffs; super-steep retrograde; surface counter doping; CMOS process; CMOS technology; Circuit simulation; Counting circuits; Energy consumption; Instruments; MOS devices; SPICE; Semiconductor device doping; Very large scale integration;
Conference_Titel :
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-3036-6
DOI :
10.1109/LPE.1995.482472
