Datapath layout optimization using OpenTS [SoC]

As more datapath stacks are integrated into system-on-chips (SOC), the datapath is becoming a critical part of the whole giga-scale integrated circuit (GSI) design. The traditional layout design methodology cannot satisfy the datapath performance requirements since it has no knowledge of the datapath bit-sliced structure. In this paper, we applied an approach of OpenTS (open tabu search) to determine the optimal datapath element ordering to minimize the track density, the wire length and interconnection delay. Experimental results show that the OpenTS is more efficient than the existing genetic and simulated annealing approaches.