• DocumentCode
    3169257
  • Title

    Efficient design and generation of a multi-facet arbiter

  • Author

    Jou, Jer Min ; Lee, Yun-Lung ; Wu, Sih-Sian

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    2010
  • fDate
    13-14 June 2010
  • Firstpage
    111
  • Lastpage
    114
  • Abstract
    Based on the arbiter template developed in, we presented an efficient, modular, and scalable decentralized parallel design of a new multi-facet arbiter. Moreover, with this modular and reusable hardware design, we have implemented a parametric arbiter generator that automatically generates various multi-facet arbiters. With the decentralized parallel design and the generator, not only a fastest and smallest round-robin arbiter but also other type arbiters were designed and generated on the fly. The experiment results were given to show the designs´ excellent performances.
  • Keywords
    asynchronous circuits; network synthesis; arbiter template; decentralized parallel design; modular hardware design; multi-facet arbiter; reusable hardware design; Bandwidth; Costs; Delay; Distributed power generation; Hardware; Resource management; Switches; Tree data structures; Upper bound; WiMAX;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Specific Processors (SASP), 2010 IEEE 8th Symposium on
  • Conference_Location
    Anaheim, CA
  • Print_ISBN
    978-1-4244-7953-5
  • Type

    conf

  • DOI
    10.1109/SASP.2010.5521137
  • Filename
    5521137