Design fast round robin scheduler in FPGA

Author

Huajin, Sun ; Deyuan, Gaa ; Shengbing, Zhang ; Danghui, Wang

Author_Institution

Aviation Microelectron. Center, Northwestern Polytech. Univ., Xi´´an, China

Volume

2

fYear

2002

fDate

29 June-1 July 2002

Firstpage

1257

Abstract

As a classical scheduling algorithm, the round robin scheduling algorithm is as widely used at present as it was in the past. A new FPGA-based implementation method is presented in this paper. After considering the FPGA structural characteristics and requirements of the system, a method using a pipelined priority encoder (PPE) and a barrel shifter (BS) is implemented effectively in an FPGA, and the performance of the PPE and BS is evaluated. The test results of the system show that the algorithm implementation is successful and fulfills the system requirements. At the same time, the method is also useful in other cases in which the round robin is applied.

Keywords

circuit simulation; field programmable gate arrays; integrated circuit design; integrated circuit modelling; logic design; logic simulation; packet switching; processor scheduling; time-sharing programs; time-sharing systems; CPU schedulers; FPGA-based fast round robin schedulers; PPE; barrel shifters; data communication cross-network packet scheduling; pipelined priority encoders; round robin scheduling algorithms; time-sharing system scheduling algorithms; Algorithm design and analysis; Digital systems; Field programmable gate arrays; Logic arrays; Logic functions; Programmable logic arrays; Round robin; Scheduling algorithm; Sun; Tail;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on

Print_ISBN

0-7803-7547-5

Type

conf

DOI

10.1109/ICCCAS.2002.1179011

Filename

1179011