Design of a system-on-chip switched network and its design support

Author

Wiklund, Daniel ; Liu, Dake

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Sweden

Volume

2

fYear

2002

fDate

29 June-1 July 2002

Firstpage

1279

Abstract

As the degree of integration increases, the on-chip communication is becoming a bottleneck. A solution to this problem is to use an on-chip switched interconnect network. Such a system-on-chip network was proposed in 2000 by the same authors. In this paper, we present the system-on-chip network in detail together with the design flow support. The choice of topology for the network, as well as some ways to use the network to overcome the future physical implementation issues of wire delay, and to gain performance, is also discussed. To aid the design choices of the network, a behavioral simulator has been created. The importance of the behavioral simulator is clearly shown from the design flow and the design and implementation of this simulator is discussed in detail.

Keywords

circuit CAD; circuit simulation; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; logic CAD; logic simulation; network topology; system-on-chip; SOC networks; behavioral simulators; design flow support; design support tools; network topology; on-chip communication; performance gain; switched interconnect networks; system-on-chip switched networks; wire delay; Communication switching; Computer networks; Concurrent computing; Delay; Hardware; Network topology; Network-on-a-chip; Switches; System-on-a-chip; Time division multiplexing;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on

Print_ISBN

0-7803-7547-5

Type

conf

DOI

10.1109/ICCCAS.2002.1179016

Filename

1179016