Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs

In nanoscale digital CMOS IC design, the large technology parameter variations have boosted the interest in statistical performance analysis. As the huge execution time of SPICE-based transistor-level Monte Carlo analysis is impractical for complex designs, there is a need for making accurate Monte Carlo analysis feasible through fast logic-level simulators. This paper presents a new, general logic model of digital CMOS cells featuring technology variation aware timing, and its prototype implementation in a standard hardware-description-language environment. The application of the approach to typical standard cells and test circuits shows very good agreement with SPICE BSIM4 transistor-level simulation both for nominal delay and for statistical Monte Carlo analyses.