Design and application of SDH pointer leakage ASIC MXTULPx8-5

The development of the synchronous digital hierarchy (SDH) technique relies on the evolution of ASICs. This paper introduces the characteristics of the SDH pointer leakage ASIC MXTULPx8-5, which has been designed independently by the E&E Department of Tsinghua University. This chip can compensate for plesiochronous relationships between incoming and outgoing higher level (AU4) synchronous payload envelope frame rates through processing of the lower level (TU11, TU12, or TU3) tributary pointers, so that the aligned tributaries can be easily column switched by the SDH tributary unit cross-connect chip. The time-sliced multiplexing design method is introduced as the key technique, and the tributary elastic buffer size is calculated. The application example of MXTULPx8-5 is also described.