Design of digital classifier circuits with nearest neighbour prior sample selection

A new method for design of digital classification circuits is presented in this paper in order to implement them in hardware (FPGA, PAL, VLSI, ASIC, etc). The method works by first selecting a subset of the training data that is just off the separation margin between the classes. The subset is provided to a Boolean minimization algorithm that, by hypercube expansion, designs a classifier with a smoother separation surface between classes. The obtained circuits have performance comparable to support vector machines and multilayer perceptron trained with a generalization control algorithm.