Stable interconnect RC model via matching the first two moments

Author

Chen, El ; Yang, Huazhong ; Luo, Rong ; Wang, Hui

Author_Institution

Dept. of Electron. & Eng., Tsinghua Univ., Beijing, China

Volume

2

fYear

2002

fDate

29 June-1 July 2002

Firstpage

1330

Abstract

Interconnect RC effect has a dominant impact on VLSI performance as the process technology moves towards the sub-micrometer regime. The delays of global interconnects are greater than those of the gates, and the analysis of interconnects becomes indispensable in VLSI design. In this paper, a stable two-pole model is given which matches not only the first two moments as traditional methods do, but adds a zero, in case of unstable conditions being encountered, into the transfer function to improve the stability. The simulation results show that this model can achieve reasonable accuracy.

Keywords

VLSI; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; poles and zeros; stability; transfer functions; VLSI design; VLSI performance; global interconnect delays; interconnect RC effect; moment matching; process technology regime; simulation; stability; stable interconnect RC model; stable two-pole model; transfer function; unstable condition; zero model addition; Contracts; Delay; Frequency; Integrated circuit interconnections; Robustness; Stability; Transfer functions; Uncertainty; Upper bound; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on

Print_ISBN

0-7803-7547-5

Type

conf

DOI

10.1109/ICCCAS.2002.1179027

Filename

1179027