A New Kind of Processor Interface for a System-on-Chip Processor with TIE Ports and TIE Queues of Xtensa LX

Today, most System-on-a-Chip (SoC) ASIC chips integrate multiple processor cores as well as hard-wired RTL blocks to realize very complex applications. While computation performance of processors increases, data throughput becomes the bottleneck. Moreover, as processors and RTL blocks need to share data and control/status, inter processors/RTL communications become a serious issue. While various system interconnects have been introduced, processor interface architecture remains conceptually the same. To overcome the communication bottleneck, this paper presents a new type of embedded processor interface for SoC design. And, as the actual realization of such an interface, the TIE ports and TIE queues of XtensaLX processor from Tensilica, Inc. is introduced in this paper.