Efficient VLSI module placement with solution space smoothing

Due to the rugged terrain surface of the search space of a placement instance, it often is stuck at a locally optimum configuration. In this paper, we propose a solution space smoothing technique for VLSI block placement. A placement instance with the simplest terrain structure is solved first, and the original problem instance with more complicated terrain structure is solved last. The solutions of the simplified problem instances are used to guide the search of more complicated ones. Compared with the simulated annealing algorithm, the solution space smoothing method needs few control parameters and the parameters are easy to determine. Experimental results of MCNC benchmarks show that solution space smoothing is very efficient for VLSI module placement. It can be applied to floorplanning representations, such as BSG, SP, CBL, B*-tree, O-tree, etc.