Data-path layout design inside SOC

As more data-path stacks are integrated into system-on-a-chip (SOC), data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design. The traditional layout design methodology can not satisfy the data-path performance requirements because it has no knowledge of the data-path bit-sliced structure and the strict performance (such as timing, coupling, and crosstalk) constraints. In this paper, we address fundamental problems in layout design automation of data-path. We concentrate on the key technologies in data-path layout design. We also discuss the corresponding researches and solutions in this research field.