Datapath allocation algorithm for deep submicron VLSI

With the feature size of VLSI scaling down, interconnect delays begin to dominate the circuit performance. Typical Top-Down High level synthesis methodology is not suitable to the deep submicron VLSI design any more. We present a novel design methodology of datapath allocation for deep submicron VLSI. After allocation, we obtain not only the datapath netlists, but also the floorplan information. Floorplan information is used to direct allocation, thus interconnect delays are efficiently optimized. Design examples are presented to help concluding that our algorithm is very efficient.