DocumentCode
3170305
Title
Performance improvements in multi-gigabit/s oversampling ADCs
Author
Frounchi, Javad ; Harrold, Steve J.
Author_Institution
Dept. of Electr. Eng. & Electron., Univ. of Manchester Inst. of Sci. & Technol., UK
fYear
1999
fDate
1999
Firstpage
9
Lastpage
12
Abstract
Design of a complete multi-GHz GaAs HEMT sigma-delta ADC is presented. A novel process insensitive technique has been applied to the design of the ΣΔ modulator and new GaAs source-follower DCFL (SDCFL) complex gates were used in the comb decimator. Simulation results of the modulator confirm that the SNR at the modulator output is relatively insensitive to variations in process parameters. Measurements on high-speed adder test circuits indicate that a speed of 2 GHz with 2.2 W power dissipation can be obtained from the decimator
Keywords
sigma-delta modulation; 2 GHz; 2.2 W; HEMT; SNR; comb decimator; high-speed adder; multi-gigabit/s oversampling ADCs; power dissipation; process insensitive technique; process parameters; sigma-delta ADC; source-follower DCFL;
fLanguage
English
Publisher
iet
Conference_Titel
Advanced A/D and D/A Conversion Techniques and Their Applications, 1999. Third International Conference on (Conf. Publ. No. 466)
Conference_Location
Glasgow
ISSN
0537-9989
Print_ISBN
0-85296-718-7
Type
conf
DOI
10.1049/cp:19990451
Filename
793952
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