TGSCO: an algorithm for topology generation of clock tree with skew constraint and optimization

In this paper, a new clock tree topology generation algorithm TGSCO is proposed for the clock routing. The optimization includes two parts: a constructive stage followed by local topology refinement. During clock tree construction, the skew relationship between clock sinks is considered. Appropriate adjustment to the topology can reduce the delay and skew further. Voronoi diagram is used to accelerate computing. Different from previous methods, our algorithm can produce a clock tree with both balanced topology and short wire length. The experimental results show that the algorithm can control the skew constraints effectively, reduce total wire length, and find an optimized clock tree.