VLSI implementation of a high-performance 32-bit RISC microprocessor

Author

Li, Xia ; Ji, Longwei ; Shen, Bo ; Li, Wenhong ; Zhang, Qianling

Author_Institution

ASIC&Syst. State Key Lab, Fudan Univ., Shanghai, China

Volume

2

fYear

2002

fDate

29 June-1 July 2002

Firstpage

1458

Abstract

The microprocessor is one of the most important blocks of the SoC. Considering high-performance, we implement a 32-bit RISC microprocessor, named as FDU32, with instruction sets compatible with ARM7TDMI. By using 5-stage pipeline and improving the circuit structure, FDU32 obtains 67% increment in max clock rate, 11% reduction in CPI and 86% increment in MIPS compared with ARM7TDMI at the same 0.35 μm CMOS process, and only the transistor count increases a little. FDU32 has passed the FPGA verification and taped out.

Keywords

CMOS digital integrated circuits; VLSI; field programmable gate arrays; microprocessor chips; pipeline processing; reduced instruction set computing; system-on-chip; 0.35 micron; 32 bit; CMOS process; FDU32; FPGA verification; RISC microprocessor; VLSI; circuit structure; instruction set; pipeline architecture; system-on-chip; Circuits; Clocks; Data processing; Instruction sets; Microprocessors; Pipelines; Reduced instruction set computing; Registers; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on

Print_ISBN

0-7803-7547-5

Type

conf

DOI

10.1109/ICCCAS.2002.1179054

Filename

1179054