A Low-Level Image Processing Algorithms Accelerator Platform

This work presents a reconfigurable computing architecture targeting a Virtex-II device. In this approach a systolic array for low-level image processing is considered. The architecture is customizable providing the possibility of performing window operations with masks of variable size and every processing element in the array can be configured according to a control word. The architecture comprises a scheme to reduce the number of accesses to data memory and router elements to handle data movement among different structures inside the same architecture, these components add the possibility of chaining interconnection of multiple processing blocks. In order to turn the architecture into a real platform, support has been provided to the motion estimation algorithm which presents higher complexity. In this modality the 2D array operates with a double ALU that allows searching multiple macro-blocks in parallel. Results using 640 times 480 gray level images show that a peak performance of 9 GOPS can be achieved.