A VLSI architecture for analog-to-residue conversion

The design of a 16-bit A/R converter using two flash converter stages, incorporating an error correction mechanism, is given in this paper. The errors are corrected by modifying the existing PLA design as well as by including a digital error correction logic. The ROM requirement is equivalent to only a total of 90 bytes and the number of module adders is 16 and single bit binary adders is 4. The design uses only 40 voltage comparators for the two flash converter stages and is implemented using low power CMOS and pass logic