• DocumentCode
    3170922
  • Title

    Design considerations for a general purpose systolic processing element using bit serial techniques

  • Author

    Gingell, M.J. ; Robertson, W. ; Phillips, W.J.

  • Author_Institution
    Atlantic Combat Syst. Eng. Div., Naval Eng. Unit, Halifax, NS, Canada
  • fYear
    1994
  • fDate
    25-28 Sep 1994
  • Firstpage
    636
  • Abstract
    The demands of modern high performance numerical applications are such that they must be met in principle by special-purpose computational architectures. Processing architectures fall into two distinct categories, serial-data and parallel-data. For fixed-function, real-time computational requirements, serial data architectures exhibit many advantages over equivalent bit-parallel architectures, especially when size and area are of primary concern. Advantages of serial data hardware include: performance and efficiency, functional parallelism, physical partitioning and testability. Single wire communication, as opposed to parallel busses, ease interconnection problems and decrease layout area. With the new technology available today, serial techniques must be seriously reconsidered
  • Keywords
    VLSI; logic CAD; logic design; systolic arrays; bit serial; functional parallelism; interconnection; layout area; performance; physical partitioning; serial data hardware; systolic processing element; testability; Design automation; Logic design; Systolic arrays; Very-large-scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on
  • Conference_Location
    Halifax, NS
  • Print_ISBN
    0-7803-2416-1
  • Type

    conf

  • DOI
    10.1109/CCECE.1994.405832
  • Filename
    405832