• DocumentCode
    3171734
  • Title

    Influence of gate offset spacer width on SOI MOSFETs HF properties

  • Author

    Valentin, R. ; Siligaris, A. ; Pailloncy, G. ; Dubois, E. ; Dambrine, G. ; Danneville, F.

  • Author_Institution
    IEMN, Villeneuve
  • fYear
    2006
  • fDate
    18-20 Jan. 2006
  • Abstract
    This work focuses on the influence of the gate spacer offset width (Loffset) on SOI MOSFET high frequency (HF) properties. For this purpose, the DC simulated results were calibrated on experimental data of a 130 nm SOI partially depleted technology. Variations of Loffset were subsequently applied to study its impact on different HF figures of merit (ft, fmax)
  • Keywords
    MOSFET; semiconductor device models; silicon-on-insulator; 130 nm; SOI MOSFET high frequency properties; SOI partially depleted technology; gate offset spacer width; parasitic capacitances; series resistances; Circuit simulation; Data mining; Equivalent circuits; Hafnium; Immune system; MOSFETs; Magneto electrical resistivity imaging technique; Parasitic capacitance; Radio frequency; Space technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-9472-0
  • Type

    conf

  • DOI
    10.1109/SMIC.2005.1587911
  • Filename
    1587911
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3171734