Title :
Technology CAD of non-volatile SONOS memory devices
Author :
Chakraborty, P. ; Mahato, S.S. ; Maiti, T.K. ; Saha, S. ; Maiti, C.K.
Author_Institution :
IIT Kharagpur, Kharagpur
Abstract :
Scaled 100-nm gate length SONOS memory devices with a nitride layer embedded in the gate stack is studied using Technology CAD (TCAD). The program and erase states of the device are simulated. Long-term (10-year) charge retention capabilities of the SONOS structure are predicted.
Keywords :
electronic design automation; random-access storage; semiconductor device models; nitride layer; nonvolatile SONOS memory devices; size 100 nm; technology CAD; CMOS technology; EPROM; Electron traps; Low voltage; Nonvolatile memory; PROM; SONOS devices; Spontaneous emission; Threshold voltage; Tunneling; Program and erase; Retention; trapped charge;
Conference_Titel :
Physics of Semiconductor Devices, 2007. IWPSD 2007. International Workshop on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4244-1728-5
Electronic_ISBN :
978-1-4244-1728-5
DOI :
10.1109/IWPSD.2007.4472479
