• DocumentCode
    3172000
  • Title

    The multiprocessor system with a fairly weighted global bus arbitration circuit

  • Author

    Deshmukh, R.G. ; Doi, S.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Florida Inst. of Technol., FL, USA
  • fYear
    1990
  • fDate
    1-4 Apr 1990
  • Firstpage
    750
  • Abstract
    The design and construction of a tightly coupled multiprocessor system and a global bus granting arbitration circuit is discussed. The prototype system performance is analyzed, and it is shown that the addition of loosely coupled system features like private input-output devices and large local memories on a tightly coupled system exhibit characteristics such as high reliability and availability, ease of expansion, ease of programming, economy, and significantly higher performance over a comparable class of uniprocessor systems
  • Keywords
    multiprocessing systems; availability; large local memories; loosely coupled system features; private input-output devices; reliability; system performance; tightly coupled multiprocessor system; weighted global bus arbitration circuit; Availability; Circuit testing; Concurrent computing; Coupling circuits; Independent component analysis; Multiprocessing systems; Performance analysis; Prototypes; Switches; System performance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Southeastcon '90. Proceedings., IEEE
  • Conference_Location
    New Orleans, LA
  • Type

    conf

  • DOI
    10.1109/SECON.1990.117917
  • Filename
    117917