Response Surface Methodology for statistical characterization of nano CMOS devices and circuits

Author

Mande, Sudhakar ; Chandorkar, A.N.

Author_Institution

IIT Bombay, Mumbai

fYear

2007

fDate

16-20 Dec. 2007

Firstpage

297

Lastpage

300

Abstract

The accurate prediction of the impact of process variations on circuit performance is very crucial in deciding the parametric yield of integrated circuits. This paper presents the simulation methodology for studying the impact of process variations on device and circuit performance in nanometer regime. In this paper, an empirical model for power and delay of 45 nm node CMOS inverter is build using the well-known response surface methodology. This work also compares the suitability of different response design in terms of model accuracy.

Keywords

CMOS integrated circuits; delay circuits; integrated circuit design; integrated circuit modelling; integrated circuit yield; invertors; nanoelectronics; response surface methodology; semiconductor device models; semiconductor process modelling; statistical analysis; CMOS inverter; delay empirical model; device process variations; integrated circuit parametric yield; nano CMOS devices; response surface methodology; size 45 nm; statistical characterization; CMOS process; CMOS technology; Circuit optimization; Circuit simulation; High K dielectric materials; Implants; MOS devices; Process design; Response surface methodology; Semiconductor device modeling; Process variability; Response Designs; Response Surface;

fLanguage

English

Publisher

ieee

Conference_Titel

Physics of Semiconductor Devices, 2007. IWPSD 2007. International Workshop on

Conference_Location

Mumbai

Print_ISBN

978-1-4244-1728-5

Electronic_ISBN

978-1-4244-1728-5

Type

conf

DOI

10.1109/IWPSD.2007.4472503

Filename

4472503