A 9 ns, low standby power CMOS PLD with a single-poly EPROM cell

Author

Frake, S. ; Knecht, M. ; Cacharelis, P. ; Hart, M. ; Manley, M. ; Zeman, R. ; Ramus, R.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1989

fDate

15-17 Feb. 1989

Firstpage

230

Lastpage

231

Abstract

The authors describe a 9-ns CMOS programmable logic device (PLD) with a standby current of 10 mu A. The circuit is a 24-pin PLD with 10 I/Os (input/outputs) and 12 dedicated inputs. Each I/O has eight summed-product terms and an output-enable control product term feeding into a programmable macrocell. Most standard 24-pin PLDs can be emulated by selectively programming the macrocell architecture bits. Bit-line precharging circuitry is used to reduce the speed degradation caused by designing for low standby current. ´Ground bounce´ is alleviated by controlling the output buffer speed. The circuit has been fabricated in a 1- mu m single-polysilicon CMOS EPROM (electrically programmable read-only memory) technology that has been optimized for speed rather than for packing density. Device and technology characteristics are summarized.<>

Keywords

CMOS integrated circuits; PROM; integrated circuit technology; logic arrays; 1 micron; 10 muA; 9 ns; CMOS; PLD; characteristics; electrically programmable read-only memory; ground bounce; low standby power; optimized for speed; polycrystalline Si; precharging circuitry; programmable logic device; programmable macrocell; single-poly EPROM cell; single-polysilicon CMOS EPROM; standby current; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Delay effects; EPROM; Packaging; Silicon; Solid state circuits; Standards development;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International

Conference_Location

New York, NY, USA

Type

conf

DOI

10.1109/ISSCC.1989.48268

Filename

48268