Two-port network modelling for hardware-in-the-loop simulators

Hardware-in-the-loop simulation(HWIL) is a well established technique for aiding rapid control prototyping and design. Nevertheless there has been very little attempt in the research literature to formalize the approach in the design of hardware-in-the-loop simulations. The purpose of this paper is to consider two port networks for modelling HWIL simulators. We demonstrate that different classess of hardware-in-the-loop simulators fit well within this theoretical framework.The work in this paper also makes a direct connection between teleoperator architectures and HWIL simulations thereby enabling the prior knowledge from a different field to be used in the future analysis and design of HWIL simulators.