• DocumentCode
    3173942
  • Title

    ESD robustness of FDSOI gated diode for ESD network design: Thin or thick BOX?

  • Author

    Benoist, Thomas ; Fenouillet-Beranger, Claire ; Perreau, Pierre ; Buj, Christel ; Galy, Philippe ; Marin-Cudraz, David ; Faynot, Olivier ; Cristoloveanu, Sorin ; Gentil, Pierre

  • fYear
    2010
  • fDate
    11-14 Oct. 2010
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    The robustness against Electrostatic Discharge (ESD) events of gated diodes, fabricated in CMOS 45nm FDSOI technology, is compared for 10nm and 145nm Buried Oxide (BOX) thickness. It is shown that the performance of devices for co-design on thin BOX is improved thanks to a better thermal dissipation: A gain of 1.6 on the robustness was found.
  • Keywords
    CMOS integrated circuits; electrostatic discharge; silicon-on-insulator; CMOS FDSOI technology; ESD network design; ESD robustness; FDSOI gated diode; buried oxide; electrostatic discharge; gated diodes; thick BOX; thin BOX; Electrostatic discharge; Logic gates; Robustness; Temperature measurement; Transmission line measurements; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference (SOI), 2010 IEEE International
  • Conference_Location
    San Diego, CA
  • ISSN
    1078-621x
  • Print_ISBN
    978-1-4244-9130-8
  • Electronic_ISBN
    1078-621x
  • Type

    conf

  • DOI
    10.1109/SOI.2010.5641372
  • Filename
    5641372
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3173942