Title :
High reliability packaging technologies and process for ultra low k Flip Chip devices
Author :
Joonyoung Park ; YunHee Kim ; SeokHo Na ; Jinyoung Kim ; ChoonHeung Lee ; Nicholls, Lou
Author_Institution :
Amkor Technol. Inc., Seoul, South Korea
Abstract :
Ultra-high density chips are required for higher device performance, lower power consumption and a smaller form factor device. The interconnection between the chip and integrated circuit (IC) reflect these higher densities, smaller feature size can induce electrical interference based on layout and material set. Therefore, when new interlayer dielectric (ILD) materials are introduced into next generation process node, the chip package interaction (CPI) must be fully characterized for process compatibility and reliability. Major foundries have used ultra-low dielectric constant (ULK) materials for higher performance devices. But ULK dielectrics have a brittle mechanical nature and are damaged easily from external mechanical or thermal stress. Moreover, as interconnection materials for flip chip devices have changed from collapsible lead-based and tin-silver (SnAg) bumps to more rigid copper (Cu) pillar bumps, the CPI risk has increased as the Cu pillar bumps induce more stress to the ULK dielectric layer. ULK devices require low-stress interconnection methods. Amkor Technology suggests a thermo-compression (TC) bonding with Non-Conductive paste (TCNCP) assembly process to reduce the stress induced between the ULK silicon stack and the substrate. TCNCP utilizes a TC bonder head and heater block for the chip and substrate that minimizes effective CTE mismatch by controlling the reflow temperature more precisely at the chip interface. Maintaining a high temperature difference between chip and substrate is essential in reducing ULK stress from the coefficient of thermal expansion (CTE) mismatch. An approximate 80% improvement in stress levels as compared to conventional mass reflow processes was demonstrated with finite element analysis (FEA) simulation and verified by reliability performance. Amkor Technology applied the TCNCP process in the assembly of a ULK die within a Flip Chip chip scale package (fcCSP). This paper reviews the TCNCP process flow as designed for th- ULK device, discusses the reliability results, and proposes guidelines for successful ULK device packaging as process technology migrates to 16/14-nm or 10-nm device nodes.
Keywords :
copper; dielectric materials; finite element analysis; flip-chip devices; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; lead; power consumption; silicon; silver alloys; tape automated bonding; thermal stresses; tin alloys; Amkor Technology; CPI risk; CTE mismatch; Cu; FEA; ILD materials; Pb; Si; SnAg; TC bonder head; TC bonding; TCNCP assembly process; TCNCP process flow; ULK device packaging; ULK devices; ULK dielectric layer; ULK materials; ULK silicon stack; ULK stress; chip interface; chip package interaction; coefficient of thermal expansion; copper pillar bumps; electrical interference; fcCSP; finite element analysis; flip chip chip scale package; heater block; high reliability packaging technologies; integrated circuit; interconnection materials; interlayer dielectric materials; lead-based bumps; low-stress interconnection methods; mass reflow processes; mechanical stress; next generation process node; nonconductive paste; power consumption; reflow temperature; thermal stress; thermocompression bonding; tin-silver bumps; ultra low k flip chip devices; ultra-high density chips; ultra-low dielectric constant materials; Bonding; Bonding forces; Integrated circuit interconnections; Performance evaluation; Reliability; Stress; Substrates;
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
DOI :
10.1109/ECTC.2015.7159562