Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste

The need for high performance and multi-functional devices drove silicon manufacturers to introduce ultra-low dielectric constant (ULK) materials into the back-end-of-line (BEOL) of silicon manufacturing. This innovative technology resulted in performance boost and low RC delay as well as reduced power consumption and cross talk. Although ULK provides electrically improved performance compared to previous generation dielectric materials, it brought significant challenge since the ULK dielectric is a porous and brittle material with inferior material properties. At the same time, advanced packaging flip chip technology is migrating from conventional mass reflow (MR) bonding processing to thermo-compression bonding using non-conductive paste (TC-NCP) to enable higher I/O counts with a smaller form factor. The combination of these trends imposes a significant chip-package interaction (CPI) challenge. Thus CPI qualification of this technology is very crucial to provide the electronics industry the confidence to adopt this technology and prepare for high volume manufacturing. In this paper, Test vehicles with various CPI structures were used to assess the CPI risks of fine pitch flip chip technology with TC-NCP bonding process. To enable efficient routing at the substrate level, a bond-on-lead (BOL) substrate was used. JEDEC Standard CPI reliability test was performed and the data was reviewed electronically and mechanically at each read-out. The test results successfully demonstrate the robustness of GLOBALFOUNDRIES´ 20-nm platform flip chip technology with Amkor Technology´s TCNCP bonding process.