Performance characterization of PD-SOI ring oscillators at cryogenic temperatures

We report on the successful operation of partially depleted silicon on insulator (PD-SOI) ring oscillators at temperatures down to 2.8 K. This 45 nm CMOS technology node hardware was fabricated on 300 mm wafers that were part of a development lot not optimized for low temperature operation. The test structure comprises a set of ring oscillators, an output multiplexer and a divide by 1024 circuit followed by an off-chip driver. By reducing the temperature of the device from 300 K to 2.8 K, the static power dissipation decreases by more than an order of magnitude. Circuit delays improve by approximately 20%, 16% from drive current enhancement and 4% from capacitance reduction. To gain further insight on this behavior we are measuring at cryogenic temperatures single MOSFETs and small arrays of MOSFETs that were fabricated alongside the ring oscillators. Experimental results and potential applications of cryogenic PD-SOI are presented.