Balanced embedded trace substrate design for warpage control

Embedded trace substrate is developed to improve both production yield and capability of substrate with fine line and space dimension. This paper presents the solution of substrate design to control warpage. Different embedded trace substrate design factors - solder resist (SR), Cu and prepreg thickness, prepreg property, maskless SR opening and Cu ratio - were led in stress simulation. On account of high modulus of Cu, the simulation results showed the balanced top/bottom copper volume and the selection of high modulus prepreg played important roles to minimize the substrate warpage performance in high temperature. Also, warpage measurement of test vehicles with varying thickness of top and bottom copper layers indicated the substrate design with balance of top and bottom copper volume had the best warpage performance among all test vehicles. Therefore, the embedded trace substrate design with balanced top/bottom Cu volume is optimal for warpage improvement.