• DocumentCode
    3175572
  • Title

    Embedded memory considerations in SOI

  • Author

    Wang, G. ; Radens, C. ; Safran, J. ; Pei, C. ; Freeman, G. ; Parries, P. ; Malik, R. ; Iyer, S.S.

  • Author_Institution
    Semicond. R&D Center, IBM, Hopewell Junction, VA, USA
  • fYear
    2010
  • fDate
    11-14 Oct. 2010
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    The transition to multicore computing demands more embedded cache memories. Incorporating high performance eDRAMs into the cache hierarchy is an attractive solution. In this paper, we discuss the roles of SRAM, eDRAM and eFUSE OTPROM in a high performance SOI chip.
  • Keywords
    DRAM chips; PROM; SRAM chips; cache storage; embedded systems; silicon-on-insulator; SOI chip; SRAM; cache hierarchy; eDRAM; eFUSE OTPROM; embedded cache memories; multicore computing; Capacitors; Doping; Performance evaluation; Random access memory; Silicon; Silicon on insulator technology; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference (SOI), 2010 IEEE International
  • Conference_Location
    San Diego, CA
  • ISSN
    1078-621x
  • Print_ISBN
    978-1-4244-9130-8
  • Electronic_ISBN
    1078-621x
  • Type

    conf

  • DOI
    10.1109/SOI.2010.5641468
  • Filename
    5641468
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3175572