Title :
Stacked devices for SEU immune design
Author :
Oldiges, P. ; Rodbell, K. ; Ning, T. ; Cai, J. ; Heidel, D. ; Tang, H. ; Wissel, L. ; Gordon, M.
Author_Institution :
Semicond. R&D Center, IBM Corp., Hopewell Junction, NY, USA
Abstract :
A stacked transistor on SOI shows the potential to provide soft error upset immune designs. Key design elements are presented and analyzed showing tradeoffs between standard SOI devices and stacked devices, as well as alternative layouts to optimize soft error upset immunity.
Keywords :
MOSFET; silicon-on-insulator; SEU immune design; SOI devices; alternative layouts; key design elements; soft error upset immune designs; soft error upset immunity; stacked devices; stacked transistor; Electric potential; Immune system; Junctions; Logic gates; MOSFET circuits; Single event upset; Transistors;
Conference_Titel :
SOI Conference (SOI), 2010 IEEE International
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-9130-8
Electronic_ISBN :
1078-621x
DOI :
10.1109/SOI.2010.5641469
