Extremely thin SOI (ETSOI) technology: Past, present, and future

Author

Cheng, K. ; Khakifirooz, A. ; Kulkarni, P. ; Ponoth, S. ; Kuss, J. ; Edge, L.F. ; Kimball, A. ; Kanakasabapathy, S. ; Schmitz, S. ; Reznicek, A. ; Adam, T. ; He, H. ; Mehta, S. ; Upham, A. ; Seo, S.-C. ; Herman, J.L. ; Johnson, R. ; Zhu, Y. ; Jamison, P.

Author_Institution

IBM Res. at Albany Nanotech, Albany, NY, USA

fYear

2010

fDate

11-14 Oct. 2010

Firstpage

1

Lastpage

4

Abstract

As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.

Keywords

CMOS integrated circuits; silicon-on-insulator; complementary metal-oxide-semiconductor integrated circuits; continued CMOS scaling; extremely thin SOI technology; mainstream technology; silicon-on-insulator; CMOS integrated circuits; Logic gates; Manufacturing; Performance evaluation; Silicon; Substrates; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference (SOI), 2010 IEEE International

Conference_Location

San Diego, CA

ISSN

1078-621x

Print_ISBN

978-1-4244-9130-8

Electronic_ISBN

1078-621x

Type

conf

DOI

10.1109/SOI.2010.5641473

Filename

5641473