Measurement and characterization of backplanes for serial links operating at 56 Gbps

The development of the next generation serial interfaces that operate between 50 Gbps and 60 Gbps is underway to deploy 400 Gb/s Ethernet systems. Design, analysis, and characterization of passive channels at these data rates are very challenging. Advanced modeling, analysis, and improved measurement techniques are required to accurately characterize high-speed links over broad frequency ranges. This paper describes the design and measurement used to characterize high-speed interconnects: boards, packages, and connectors including transition structures. Various interconnect components including several boards with various PCB laminates, backplanes with one and two connectors, straight through and orthogonal midplanes, chip-to-chip, and chip-to-module systems with transmitter and receiver packages are built and measured. Since both NRZ and PAM-4 signaling are presently under consideration for these new interfaces, the optimized interconnects are then analyzed using various equalization and these two signaling techniques at data rate of 56 Gbps. The resulting link performance is provided for the measured interconnect systems.