A look at parallel operations in division

Methods of implementing division are considered in terms of reducing the time required per iteration and the number of iterations required in a system which includes parallel operations. Several division schemes are described and an evaluation measure is proposed and is used to evaluate them. Specifically, a byte division and two series expansions are considered. The analysis of these options is based on an arithmetic unit which provides for parallel data paths and operations. The arithmetic unit includes a pipelined multiplier, an adder, a lookup table, and a limited amount of specialized logic. Additionally, two data buses are provided to avoid waiting on a data path. The use of a pipelined multiplier which can have two multiplications in progress results in some delay while waiting for a multiplier. However, the speed improvement for two separate multipliers would not offset the additional chip area required. The specialized functions required are described