Monolithic integration of III–V HEMT and Si-CMOS through TSV-less 3D wafer stacking

III-V compound semiconductor HEMT integrated with silicon CMOS on a silicon common substrate is promising to open up new circuit applications and capabilities. In the conventional hybrid approach, silicon and III-V circuits are fabricated and packaged separately, and then assembled on a carrier substrate. This approach is confronted by interconnect size and losses, which affect performance, form factor, power consumption, cost, and complexity. For III/V-Si hybrid integration, direct epitaxial growth of III-V compounds on Si substrate or CMOS devices would be the most desirable approach, but the high temperature III-V materials growth would severely degrade the CMOS transistors. 3D wafer stacking combining bonding and layer transfer, on the other hand, is another promising approach to integrate III-V materials on Si substrate. In this work, 3D wafer stacking is used to integrate III-V and silicon on a common platform to realize a novel side-by-side hybrid circuit without the need for through silicon via (TSV). Integration of III-V materials (InGaAs and GaN) and SOI-CMOS on a common 200 mm Si substrate is demonstrated. The SOI-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the SOI-CMOS containing handle wafer. Oxide to oxide bonding is used as a bonding medium in this case. Various oxide to oxide bonding combinations (e.g. thermal oxide bond to PECVD SiO₂ and PECVD SiO₂ bond to PECVD SiO₂) will be discussed and the counter-measures will be implemented. Post-bonding annealing of the bonded wafer pair is carried out at 300 °C in an atmospheric N₂ ambient for 3 hours to further enhance the bond strength to > 1200 mJ/cm². Finally, a void free SOI-CMOS on III-V/Si hybrid structure on a common substrate can be realized after the handle wafer is released.