DocumentCode
3176317
Title
Survey on Formal Verification Methods for Digital IC
Author
Wang, Jianhua ; Shao, Jingbo ; Li, Yingmei ; Ding, Jinfeng
Author_Institution
Coll. of Comput. Sci. & Inf. Eng., Harbin Normal Univ., Harbin, China
fYear
2009
fDate
21-22 Dec. 2009
Firstpage
164
Lastpage
168
Abstract
This paper presents a survey of the state-of-art of formal verification technique. The expression models for formal verification are introduced and analyzed. The characteristics of each model are expounded. Moreover, the typical model checking techniques are studied. Equivalence checking and property checking are introduced. The development trend for formal verification is discussed.
Keywords
formal verification; theorem proving; digital IC; equivalence checking; formal verification; integrated circuits; model checking techniques; property checking; Circuit synthesis; Computational modeling; Design engineering; Digital integrated circuits; Educational institutions; Formal verification; Graphics; Integrated circuit modeling; Manufacturing processes; Transistors; equivalence checking; formal verification; property checking; theorem proving;
fLanguage
English
Publisher
ieee
Conference_Titel
Internet Computing for Science and Engineering (ICICSE), 2009 Fourth International Conference on
Conference_Location
Harbin
Print_ISBN
978-1-4244-6754-9
Type
conf
DOI
10.1109/ICICSE.2009.46
Filename
5521611
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