A TSV-less PoP packaging structure for high bandwidth memory

As society goes to mobile, data bandwidth is required to increase every year. Memory industry community is responsible for products like DDR3, DD4 and for mobile LPDDR3 and LPDDR4, etc. However, the products launching speed do not match well with the industry requirements. Hence revolutionary specs, such as HBM, HMC, and wide I/O 1 and wide I/O 2 have been proposed. However, to realize these memory products, TSV is needed. Even though samples have been delivered but the high price of TSV prevent wide spread use of these innovative memory products. We have developed technologies of SHCP which can support PoP I/Os more than two thousands (ECTC 2014). But in order to reduce the power, lower the operation frequency; higher I/O is more desirable to provide the same bandwidth memory performance. In this paper, we have enhanced the SHCP technology that can increase I/Os from two thousands to three thousands. In our previous ECTC paper, the target is PoP applications for memory and application processer. However, in this paper, we target stacking the same memory device on top of each other which is very similar to the stacking of HMC using TSVs. This technology can provide alternative solutions to TSV of HMC and HBM. It can also serve as backbone of 3D packaging structure. We route the connection wires to the peripheral area of the memory package and to make the connection of top memory chip to the bottom memory chip. The pitch of memory connection in this study is 0.07 mm, which is considerable smaller than the pitch of 0.3 mm used in the leading industry. The effect of coplanarity is very important during the 3D memory structure assembly. In this paper, we shall build a substrate which has pitch of 0.1 mm and that can support over 4000 I/Os. Later we shall evaluate the assembly technologies of these 3D memory packages.