Single-release-layer process for temporary bonding applications in the 3D integration area

One of the key aspects in 3D technology today is the bonding/debonding of a device wafer to a carrier wafer to enable wafer thinning and subsequent backside processing before 3D assembly. Not only must the ability of the bonding material to be very uniform in thickness across the wafer after bonding be considered, but also the ease of debonding from the carrier wafer. For the latter, a room temperature and low-force mechanical debonding technique is one of the preferred approaches and the focus of most of the semiconductor players today. The next generation of materials (BrewerBOND^® materials proposed by Brewer Science) combined with a single-release-layer process opens up new opportunities. Such materials offer a higher thermal stability during backside processing as compared to the current generation and present a higher solubility in solvent for improved post-debonding cleaning. Moreover, the single-release-layer carrier process strongly simplifies the carrier preparation as it reduces the overall number of steps required for surface preparation. A full process evaluation on active device wafers containing high frontside topography and through-silicon-vias (TSV) is described here. A process comparison with the existing ZoneBOND^® process is also proposed in terms of cost of ownership: an overall cost reduction of about 20% is calculated when a single-release-layer process is used, which includes carrier preparation and debonding process costs.