DocumentCode
3177209
Title
Design of high-rate long-length structured QC-LDPC with good error performance
Author
Yin, Xiong ; Zheng, Zhaoxia ; Dan, Yi ; Liu, Zhenglin
Author_Institution
Dept. of Electron. Sci. & Technol., HuaZhong Univ. of Sci. & Technol., Wuhan, China
fYear
2011
fDate
12-14 Dec. 2011
Firstpage
1
Lastpage
4
Abstract
In order to improve error performance of data storage, this paper presents a code-design algorithm for a class of structured quasi-cyclic low-density parity-check (SQC-LDPC) codes with high rate ( R >;= 0.9 ) and long-length (104 <; 60 n). In the design of parity-check matrix, optimized degree distribution pairs are obtained based on the combination of density evolution and differential evolution with a modified cost function. Moreover, both fewer short block-cycles and larger approximated cycle extrinsic message degree (ACE) are also considered. Simulation results indicate that codes in this design method its simulation curve is close to Shannon limit and have lower error floor.
Keywords
cyclic codes; parity check codes; SQC-LDPC code; Shannon limit; code-design algorithm; cost function; cycle extrinsic message degree; data storage; density evolution; differential evolution; error floor; error performance; high-rate long-length structured QC-LDPC; optimized degree distribution; parity-check matrix; short block-cycle; simulation curve; structured quasicyclic low-density parity-check code; Algorithm design and analysis; Cost function; Encoding; Filling; Floors; Parity check codes; Simulation; ACE; SQC-LDPC; error floor; high-rate; long-length;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing and Communication Systems (ICSPCS), 2011 5th International Conference on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4577-1179-4
Electronic_ISBN
978-1-4577-1178-7
Type
conf
DOI
10.1109/ICSPCS.2011.6140871
Filename
6140871
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