Modeling and analyzing NBTI in the presence of Process Variation

With continuous scaling of transistors in each technology generation, NBTI and Process Variation (PV) have become very important silicon reliability problems for the micro processor industry. In this paper, we develop an analytical model to capture the impact of NBTI in the presence of PV for use in architecture simulations. We capture the following aspects in the model: i) variation in NBTI related to stress and recovery due to workloads, ii) temporal variation in NBTI due to Random Charge Fluctuation (RCF) and iii) Random Dopant Fluctuation (RDF) due to process variation. We use this model to analyze the combined impact of NBTI and PV on a memory structure (register file) and a logic structure (Kogge-Stone adder). We show that the impact of the threshold voltage variations due to NBTI and PV over the nominal degradation can hurt the yield of the structures. Due to the combined effect of NBTI and PV across different benchmarks, 26 to 117 bits fail in a 8Kb size register file and the execution delay increases by 18% to 28% in a Kogge-Stone adder. We then discuss the implications of these results for architecture-level reliability techniques.