DocumentCode :
3177530
Title :
Self-aligned double patterning (SADP) layout decomposition
Author :
Mirsaeedi, Minoo ; Torres, J. Andres ; Anis, Mohab
Author_Institution :
ECE Dept., Univ. of Waterloo, Waterloo, ON, Canada
fYear :
2011
fDate :
14-16 March 2011
Firstpage :
1
Lastpage :
7
Abstract :
Double patterning lithography (DPL) is the most likely manufacturing process for sub-32nm technology nodes; however, there are several double patterning strategies each of which exhibits different layout decomposition challenges. Self-aligned double patterning (SADP) has attracted much interest due to its robustness against overlay errors, but SADP compliance depends strongly on the characteristics of the individual masks generated during the layout decomposition. This work establishes SADP decomposition requirements and proposes a litho-friendly layout decomposition method. First, we explain the main parameters that limit printability of SADP decomposed layouts. In-silico experiments indicate that layout patterns which are printed by the Trim mask may experience the highest levels of image transfer sensitivity. For that reason, these patterns should be assisted by sidewalls of spacer patterns which are robustly printed. Next, we present an ILP-based decomposition method which avoids decomposition conflicts and sensitive Trim edges simultaneously. Our experiments on several industrial designs reveal that the proposed method decreases the total length of sensitive Trim patterns and consequently reduces the overall edge placement error significantly.
Keywords :
manufacturing processes; masks; nanopatterning; photolithography; semiconductor industry; ILP-based decomposition method; SADP compliance; SADP decomposed layout printability; Trim mask; double patterning lithography; edge placement error; image transfer sensitivity; litho-friendly layout decomposition method; manufacturing process; self-aligned double patterning layout decomposition; sensitive Trim edges; size 32 nm; Dielectrics; Layout; Lithography; Robustness; Sensitivity; Surface topography; Surface treatment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2011 12th International Symposium on
Conference_Location :
Santa Clara, CA
ISSN :
1948-3287
Print_ISBN :
978-1-61284-913-3
Type :
conf
DOI :
10.1109/ISQED.2011.5770711
Filename :
5770711
Link To Document :
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