Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations

CAM devices generate excessive and simultaneous current through NOR circuits during a comparison operation because of the parallel comparisons for all bits in the CAM. The ground bounce noise can be severe due to the parasitic inductance in the paths to the system ground, such as the metal lines in the CAM power structure, package pins, and system board. The ground bounce noise can cause subtle failures unless carefully considered as a key design parameter. The simultaneous current largely depends on the number of stored bits matching compared data. Traditionally, the NOR circuit in the CAM is perceived to respond faster when the transistors to the ground path in the circuit are active. However, this work shows that this notion can be greatly misleading when the ground bounce effects are not considered. The design method of the comparison cells is newly proposed to meet the optimal CAM evaluation time by simultaneously considering operational speed, extreme case analyses of the NOR circuit, and ground bounce noises. The proposed design method effectively provided the optimal design decision, which could be otherwise misleading if no ground bounce effect is considered. We demonstrated in sample designs that the proper choice of comparison-cell size reduced evaluation time by 54.9% while reducing comparison-cell size by 57.1% when ground bounce effects were considered.