• DocumentCode
    3178389
  • Title

    Ternary circuits for Null Convention Logic

  • Author

    Andrawes, Sameh ; Beckett, Paul

  • Author_Institution
    Electr. & Comput. Eng., RMIT Univ., Melbourne, VIC, Australia
  • fYear
    2011
  • fDate
    Nov. 29 2011-Dec. 1 2011
  • Firstpage
    3
  • Lastpage
    8
  • Abstract
    Null Convention Logic (NCL) adds a control value (NULL i.e., DATA not valid) to its Boolean set to create a symbolically complete logic system that is inherently self determined, locally autonomous, self synchronizing and delay insensitive. NCL circuits typically employ a dual-rail binary scheme to represent these three levels. In this paper, we propose using an offset ternary logic system where the logic set {1, N, 0} maps to voltage levels {+VDD, VDD/2, 0V}. Low-power circuits for basic components such as DATA/NULL Detector circuit and a Ternary Register are described based on the characteristics of a commercial silicon-on-sapphire MOS process that offers multiple simultaneous transistor thresholds.
  • Keywords
    detector circuits; logic circuits; ternary logic; transistor circuits; Boolean set; DATA-NULL detector circuit; NCL circuit; dual-rail binary scheme; null convention logic; offset ternary logic system; ternary circuit; ternary register; transistor threshold; Clocks; Silicon; Asynchronous; Delay Insensitive; Low-power; Multithreshold; NCL; Ternary;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Engineering & Systems (ICCES), 2011 International Conference on
  • Conference_Location
    Cairo
  • Print_ISBN
    978-1-4577-0127-6
  • Type

    conf

  • DOI
    10.1109/ICCES.2011.6141003
  • Filename
    6141003